On the Design of Reliable Boolean Circuits that Contain Partially Unreliable Gates

We investigate a model of gate failure for Boolean circuits in which a faulty gate is restricted to output one of its input values. For some types of gates, the model (which we call the short-circuit model of gate failure) is weaker than the traditional von Neumann model where faulty gates always output precisely the wrong value. Our model has the advantage that it allows us to design Boolean circuits that can tolerate worst-case faults, as well as circuits that have arbitrarily high success probability in the case of random faults. Moreover, the short-circuit model captures a particular type of fault that commonly appears in practice, and it suggests a simple method for performing post-test alterations to circuits that have more severe types of faults. A variety of bounds on the size of faulttolerant circuits are proved in the paper. Perhaps, the most important is a proof that any k-faulttolerant circuit for any input-sensitive function using any type of gates (even arbitrarily powerful, multiple-input gates) must have size at least Cl(&). Obtaining a tight bound on the size 'Research supported by AFOSR Contract F49620-92J-0125, DARPA Contract N00014-91-J-1698, and DARPA Contract N00014-924-1799. Yuan Ma is also supported by an NSF Mathematical Sciences Postdoctoral Research Fellowship. His current address is Department of Computer Science, Stanford University, Stanford, CA 94305. The authors' email: djkQmath.mit.edu, [email protected], and y [email protected] t anford. edu . of a circuit for computing the AND of two values if up to IC of the gates are faulty is one of the central questions left open in the paper.